INTERACTIVE DISTRIBUTED SYSTEMS LAB
Architecture Simulators & Interactive Visualizers
Hands-on interactive laboratories to internalize hardware latency physics, hash rings, load balancing algorithms, rate limiting buckets, Raft quorums, cryptographic handshakes, and database indexing.
Latency Numbers Visualizer ⏱️
Scale nanosecond hardware delays into intuitive human time (1 CPU cycle = 1 second).
1 CPU Clock Cycle (3.3 GHz)
0.3 ns1 Second
L1 CPU Cache Reference
0.9 ns3 Seconds
Branch Misprediction Penalty
3.0 ns10 Seconds
L2 CPU Cache Reference
4.5 ns15 Seconds
Mutex Lock / Unlock
17.0 ns1 Minute
Main Memory Reference (DRAM)
100 ns5.5 Minutes
Read 1 MB Sequentially from RAM
3,000 ns (3 μs)2.8 Hours
NVMe SSD Random Read
16,000 ns (16 μs)15 Hours
Read 1 MB Sequentially from NVMe SSD
200,000 ns (200 μs)8 Days
Intra-Datacenter Network RTT
500,000 ns (0.5 ms)19 Days
Mechanical HDD Disk Seek
8,000,000 ns (8 ms)10 Months
Cross-Atlantic Network RTT (US to Europe)
150,000,000 ns (150 ms)16 YEARS
cpu Tier0.3 ns
1 CPU Clock Cycle (3.3 GHz)
The fundamental heartbeat of modern silicon processors executing a single instruction.
Human Time Analogy (1 CPU Cycle = 1 Sec)
1 Second
If fetching from CPU register takes 1 second, this operation feels like waiting 1 Second to the processor!
💡 Architectural Insight:
Reading from RAM is like a 5-minute coffee break; reading from spinning disk is waiting 10 months; cross-ocean network calls are a 16-year career!